View SDA2586-5_252026.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Nonvolatile Memory 8-Kbit E2PROM with I2C Bus Interface
SDA 2586-5
Preliminary Data
MOS IC
Features
q Word-organized, reprogrammable nonvolatile memory in q q q q q q q q
n-channel floating-gate technology (E2PROM) 1024 x 8-bit organization Supply voltage 5 V Serial 2-line bus for data input and output (I2C Bus) Reprogramming mode, 10 ms erase / write cycle Reprogramming by means of on-chip control (without external control) The end of the programming cycle can be checked Data retention in excess of 10 years More than 104 reprogramming cycles per address
P-DIP-8-1
Type SDA 2586-5 Circuit Description I2C Bus Interface
Ordering Code Q67100-H5101
Package P-DIP-8-1
The I2C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits. It consists of a data line SDA and a clock line SCL. The data line require an external pull-up resistor to VCC (open drain output stages). The possible operational states of the I2C Bus are shown in figure 1. In the quiescent state, both lines SDA and SCL are high, i.e. the output stages are disabled. As long as SCL remains "1", information changes on the data bus indicate the start or the end of a data transfer between two components. The transition on SDA from "1" to "0" is a start condition, the transition from "0" to "1" a stop condition. During a data transfer, the information on the data bus will only change when the clock line SCL is "0". The information on SDA is valid as long as SCL is "1". In conjunction with an I2C Bus system, the device can operate as a receiver, and as a transmitter (slave receiver/listener, or slave transmitter/talker). Between a start and a stop condition, the information is always transmitted in byte-organized form. Between the falling edge of the eighth transmission pulse and a ninth acknowledge clock pulse, the device sets the SDA-line to low as a reception confirmation, if the chip select conditions have been met. During the output of data, the data output of the memory becomes high in impedance during the ninth clock pulse (acknowledge master). The signal timing required for the operation of the I2C Bus is summarized in figure 2.
Semiconductor Group
41
07.94
SDA 2586-5
Control Functions of the I2C Bus The device is controlled by the controller (master) via the I2C Bus in two operating modes: read cycle, and reprogramming cycle, including erase and write to a memory address. In both operating modes, the controller, as transmitter, has to provide 3 bytes to the bus after the start condition. Each byte has to be followed by an acknowledge bit. During a memory read, at least eight additional clock pulses are required to accept the data from the memory, before the stop condition may follow. In the programming instance, the active programming process is only started by the stop condition after data input, see figure 3. The chip select word includes the chip select bit CS. Thus it is possible to parallel two memory devices. Chip select is obtained when the control bits logically correspond to the condition selected at the select input CS. The two most significant bits A8 and A9 are inputs with the chip select words CS/E. Checking the End of the Programming Cycle and Breaking off the Programming Cycle Addressing the chip by the input of CS/E during active reprogramming terminates the programming cycle. If the chip is addressed by entering CS/A, this will be ignored. Only when the programming cycle has terminated will the chip react on CS/A. With this procedure the end of the programming cycle can be checked, see figure 3. Memory Read After the input of the two control words CS/E and WA, the resetting of the start condition and the input of a third control word CS/A, the memory is set ready to read. During acknowledge clock No. 9, the memory information is transferred in parallel to the internal data register. Subsequent to the falling edge of the acknowledge clock the data output is low-impedance and the first data bit can be sampled, see figure 4. With each shift clock, an additional bit reaches the output. After reading a byte, the internal address counter is automatically incremented through the master receiver acknowledge, so that any number of memory locations can be read one after the other. At address 1024, an overflow to address 0 is initiated. With the stop condition, the data output returns to highimpedance mode. The internal sequence control of the memory component is reset from the read to the quiescent state with the stop condition.
Semiconductor Group
42
SDA 2586-5
Memory Reprogramming The reprogramming cycle of a memory word comprises an erase and a subsequent write process. During erase, all eight bits of the selected word are set into "1" state. During the write process, "0" states are generated according to the information in the internal data register, i.e. according to the third input control word. After the 27th and the last clock of the control word input, the active programming process is started by the stop condition. The active programming process is executed under on-chip control and can be terminated by addressing the device via SCL and SDA. The time required for reprogramming depends on component deviation and data patterns. Therefore, with rated supply voltage the erase/write process is max. 20 ms, or typically, 10 ms. For the input of a data word without write request (write request is defined as data bit in the data register set to "0"), the write process is suppressed and the programming time is shortened. During a subsequent programming of an already erased memory address, the erase process is suppressed again, so that the reprogramming time is also shortened. Switch-On and Chip Reset After the supply voltage VCC has been connected, the data output will be in the high impedance mode. As a rule, the first operating mode to be entered should be the read process of a word address. Subsequent to the data output and to the stop condition, the internal control logic is reset. In the case of a subsequent active programming operation, however, the stop condition will not reset the control logic. Chip Erase To erase the entire memory the control word CS/E is entered, the address register is loaded with address 0 and the data register with FF (hex), respectively. Immediately prior to generating the stop condition, the input TP2 is connected from 0 to 5 V. The subsequent stop condition initiates the chip erase. As soon as the erase procedure has terminated, TP2 is again connected to 0 V.
Semiconductor Group
43
SDA 2586-5
Pin Configuration (top view)
Pin Definitions and Functions Pin No. 1 2 3 4 5 6 7 8 Symbol Function Ground Chip select to VSS 0 V normal function, TP2 = 5 V condition to erase of the entire memory Data line Clock line open Supply voltage
VSS
CS TP1 TP2 SDA SCL TP3
VCC
Semiconductor Group
44
SDA 2586-5
VCC
/
Block Diagram
Semiconductor Group
45
SDA 2586-5
Absolute Maximum Ratings Parameter Supply voltage Input voltage Power dissipation Storage temperature Thermal resistance (system-air) Junction temperature Operating Range Supply voltage Ambient temperature Symbol min. Limit Values max. 6 6 130 - 40 125 100 85 V V mW C K/W C - 0.3 - 0.3 Unit
VCC VI PD Tstg R th SA Tj
VCC TA
4.75 0
5.25 70
V C
Semiconductor Group
46
SDA 2586-5
Characteristics TA = 25 C Parameter Supply voltage Supply current Inputs Input voltage SDA/SCL Input voltage SDA/SCL Input current SDA/SCL Outputs Output current SDA Leakage current SDA Inputs Input voltages CS/TP1/TP2 Input voltages CS/TP1/TP2 Input currents CS/TP1/TP2 Clock frequency Reprogramming duration Input capacity Total erase Symbol min. Limit Values typ. 5.0 max. 5.25 20 V mA 4.75 Unit Test Condition
VCC ICC
VCC = 5.25 V
VIL VIH IIH
3.0
1.5
V V A
VCC
10
VIH = VCC
IQL IQH
3.0 10
mA A
VQL = 0.4 V VQH = VCC max
VIL VIH IIH fSCL tPROG C1 tGL
10 4.5
0.2
V V A kHz ms pF ms TP2 = 5 V erase and write
VCC
100 100 20 10 20
VCC = 5.25 V
Semiconductor Group
47
SDA 2586-5
Test Circuit
Application Circuit
Semiconductor Group
48
SDA 2586-5
Diagrams
Figure 1 Operational States of the I2C Bus
Figure 2 Time Conditions for the I2C Bus (high-speed mode) Semiconductor Group 49
SDA 2586-5
Timing Conditions Parameter Minimum time the bus must be free before a new transmission can start Start condition hold time Clock low period Clock high period Start condition set-up time, only valid for repeated start code Data set-up time Rise time of both the SDA and SCL line Fall time of both the SDA and SCL line Stop condition set-up time Symbol min. Limit Values max. s s s s s ns 1 300 4.7 s s s Unit
tBUF tHD;STA tLOW tHIGH tSU;STA tSU;DAT tR tF tSU;SPO
4.7 4.0 4.7 4.0 4.7 250
Note that a transmitter must internally provide at least a hold time to bridge the undefined region (max. 300 ns) of the falling edge of SCL. All values refer to VIH and VIL level.
Semiconductor Group
50
SDA 2586-5
Figure 3 Programming Control word input ST CS/E As WA As DE As SP (the reprogramming starts after this stop condition)
Check for program end by
ST
CS/A
As
1. when As = 1 programming is not finished 2. when As = 0 programming is finished
Programm interruption by Figure 4 Read Control word input read a) complete (with word address input) ST CS/E As WA As ST CS/A As DA n bytes
ST
CS/E
As
Am
DA Last byte
Am
SP
Automatic incrementation of the word address b) shortened: Bit 0 ... 9 the last adapted word address keep unchanged
ST
CS/A
As
DA n bytes
Am
DA Last byte
Am
SP
Autoincrement before stop condition
Am = 0 Am = 1
Semiconductor Group
51
SDA 2586-5
Control Word Table Clock No. CS/E CS/A WA DE DA 1 1 1 A7 D7 D7 2 0 0 A6 D6 D6 3 1 1 A5 D5 D5 4 0 0 A4 D4 D4 5 A9 - A3 D3 D3 6 A8 - A2 D2 D2 7 CS CS A1 D1 D1 8 0 1 A0 D0 D0 9 0 0 0 0 0/1 (Acknowledge) through memory through memory through memory through memory through master
Control Word Input Key CS/E CS/A WA DE DA D0 to D7 ST SP As Am CS A0 to A9 Chip select for data input into memory (with word-address bit A8 and A9) Chip select for data output out of memory Memory word address Data word for memory Data word read out for memory Data bits Start condition Stop condition Acknowledge bit from memory Acknowledge bit from master Chip select bits Memory word address bits
Semiconductor Group
52

▲Up To Search▲

Price & Availability of SDA2586-5

	To Download SDA2586-5 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .